P6 microarchitecture

Tag: p6-microarchitecture

Aliases: P6, Pentium Pro microarchitecture

Intel's value-based out-of-order microarchitecture (Pentium Pro / II / III / M) that combines Tomasulo-style reservation stations with a separate reorder buffer to support precise interrupts. Tags are ROB indices; the Map Table carries a 'ready-in-ROB' bit so dispatch can pull completed-but-not-yet-retired values directly out of the ROB.

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